1. Field of the Invention
The present invention relates to display devices, and more particularly to a high performance thin film transistor (TFT) and a method with a low mask count process for fabricating the same.
2. Description of the Related Art
The design of larger area, higher resolution, and full color Liquid Crystal Displays (LCDs) may include problems such as incomplete pixel charging, increasing pixel voltage error, signal delay, flicker, or/and crosstalk, etc. The most widely incorporated technology today for LCDs is hydrogenated amorphous silicon (a-Si:H) as the active material of the transistor.
For full color representation, unsaturated regions of the LC brightness-voltage (B-V) characteristics curve must be utilized, and brightness is easily affected by a small change in voltage applied to the liquid crystal. In thin film transistors (TFTs), voltage distortion (dVs) induced by a gate-source capacitance coupling occurs when the gate voltage changes from the on state to the off state. Consequently, degradation display quality, such as gradation of brightness and sticking images, results.
One solution of this problem includes the minimization; of the parasitic capacitances associated with the TFT""s overlapping source and drain electrodes. The reduction of these parasitic capacitances may also provide an area reduction of the designed storage capacitance, which in turn will increase a fill factor ratio.
Another concern for large content displays is proper pixel charging during the available scan time. During the scan time, the TFT xe2x80x9cONxe2x80x9d current must fully charge the LC pixel capacitance to the appropriate gray scale voltage. The TFT xe2x80x9cONxe2x80x9d current is established by the accumulation of electrons in the channel, and is intrinsically limited by the electron mobility of this material in the extended states.
Another concern, for flat panel displays competing in the monitor market which is presently dominated by mature cathode ray tube (CRT) technology, is reducing the active matrix LCD (AMLCD) cost of manufacturing. Today""s a-Si:H TFT AMLCD fabrication processes require five to six photolithographic steps. The fabrication cost of the active matrix is approximately proportional to the number of photo lithographic steps. To date, no AMLCD manufacturer is known to be practicing a 4 mask process due to such reasons as the sacrifice in either yield and/or TFT performance (and hence display performance).
Therefore, a need exists for a high performance TFT structure which alleviates the problems and issues described above. A further need exists for a TFT structure which provides a coplanar source and drain-to-gate self-aligned a-Si:H TFT and/or source and drain n+a-Si:H junctions which are directly adjacent to and contacting an accumulated channel. A further need exists for a method of manufacturing a display device which reduces a number of mask steps without reducing yield.
A transistor, in accordance with the present invention includes a gate electrode layer formed on a substrate and an insulating layer formed on the gate electrode layer. A first conductive layer forms a first portion and a second portion separated by a gap therebetween. The gap is formed at a position corresponding to a gate electrode in the gate electrode layer. A doping layer is formed on the first portion and the second portion of the first conductive layer forming a source and a drain for the transistor. A semiconductor layer is formed over the doping layer of the first portion and the second portion and in the gap in contact with the insulating layer such that upon activation of the gate electrode current flows across the gap directly between the first portion and the second portion in the first conductive layer.
Another transistor, in accordance with the invention, includes a gate electrode layer formed on a substrate and an insulating layer formed on the gate electrode layer. A doping layer has a first portion and a second portion separated by a gap therebetween. The gap is located at a position corresponding to a gate electrode in the gate electrode layer. The first portion and the second portion form a source and a drain for the transistor. A first conductive layer is formed on the doping layer and recessed back from the gap. The conductive layer forms a source electrode and a drain electrode on opposite sides of the gap. A semiconductor layer is formed over the doping layer in a region where the first conductive layer is recessed back from the gap and in the gap in contact with the insulating layer such that upon activation of the gate electrode current flows across the gap directly between the source electrode and the drain electrode.
In alternate embodiments, the first and second portions may include at least a portion formed directly on the insulating layer. The substrate may include glass, and the gate electrode layer may include an opaque metal layer. The insulating layer may include at least one of a nitride, and an oxide. The semiconductor layer may include one of amorphous silicon, polycrystalline silicon, and an organic semiconductor material. The semiconductor layer may include pentacene. The first conductive layer may include a transparent conductor. The doping layer may include doped amorphous silicon. The transistor may include a thin film transistor structure, and the doping layer may include source and drain doped junctions which are directly adjacent to and contacting the semiconductor, layer which forms an accumulated channel in the gap. The semiconductor layer in the gap is preferably substantially free from dopants. The gate electrode may include tapered edges to improve step coverage over the gate electrode. The source and drain electrodes may include tapered edges to improve step coverage over the source and drain. The source electrode or the drain electrode may include a pixel electrode for a liquid crystal display.
A method for fabricating a thin-film transistor (TFT), in accordance with the present invention, includes forming a gate electrode on a substrate, depositing insulation material on the substrate over the gate electrode and depositing a layer of conductive material on the first layer of insulation material and etching the deposited conductive layer to form a source electrode and a drain electrode spaced apart by a gap. The gap corresponds to a position of the gate electrode. A doping layer is deposited on at least a portion the source and drain electrodes. A layer of semiconductor material is deposited on the doping layer on the portions of the source and drain electrodes and the gate insulation material in the gap between the source electrode and the drain electrode such that an accumulated channel forms in the semiconductor material when the TFT is activated by the gate electrode.
In other methods, the step of depositing a layer of second insulation material on the semiconductor material may be included. The method may further include the step of etching a pattern through the second insulation material, through the semiconductor material, and through the doping layer, and terminating into one of the source electrode, drain electrode and the first layer of insulator material. The method may further include the step of forming a data line which connects to at least one of the source electrode the drain electrode, an interconnect between the data line and the gate electrode layer and a storage capacitance electrode. The first conductive material may be transparent. The method preferably consists of four masking steps. The semiconductor material may include at least one of amorphous silicon, amorphous germanium, polycrystalline silicon and organic material. The doping layer may be doped with phosphorus and the step of selectively treating the doping layer with phosphine in a plasma enhanced chemical vapor deposition process may be included.
Another method for fabricating a thin-film transistor (TFT), in accordance with the present invention, includes the steps of forming an opaque gate electrode on a substrate, depositing a first insulation material on the substrate over the gate electrode, depositing a doping layer on the first insulating material and forming a gap in the doping layer corresponding to a position of the gate electrode, depositing a conductive layer and etching the conductive layer to form a source electrode and a drain electrode by employing the gate electrode as a mask to self-align the source electrode and the drain electrode to the gate electrode, and depositing a layer of semiconductor material on the doping layer between the source electrode and the drain electrode and the first insulation material in the gap such that an accumulated channel forms in the semiconductor material when the TFT is activated by the gate electrode.
In other methods, the step of depositing a second layer of insulation material on the semiconductor material may be included. The method may include the step of etching a pattern through the second insulation material, through the semiconductor material and through the doping layer and terminating in one of the conductive layer and the first insulator material. The method may further include the step of depositing a layer of transparent conductive material and etching the transparent conductive material to form at least one of a pixel electrode and a redundant data line. The method may include the step of depositing a conductive layer and etching the conductive layer to form a source electrode and a drain electrode by employing the gate electrode as a mask to self-align the source electrode and the drain electrode to the gate electrode may include the steps of depositing the conductive layer as a layer of transparent conductive material on the first insulation material, employing a positive resist and top illumination exposure to remove unwanted transparent conductive material regions, and etching the transparent conductive material using a negative resist and back illumination exposure to self-align the source electrode and the drain electrode to the gate electrode.
In still other methods, the semiconductor material may include at least one of amorphous silicon, amorphous germanium, polycrystalline silicon and organic material. The doping layer is doped with phosphorus and may further include the step of selectively treating the doping layer with phosphine in a plasma enhanced chemical vapor deposition process.